Chapter 1 Welcome to VLSI

1.1 A Brief History

1.2 Preview

1.3 MOS Transistors

1.4 CMOS Logic

1.4.1 The Inverter

1.4.2 The NAND Gate

1.4.3 CMOS Logic Gates

1.4.4 The NOR Gate

1.4.5 Compound Gates

1.4.6 Pass Transistors and Transmission Gates

1.4.7 Tristates

1.4.8 Multiplexers

1.4.9 Sequential Circuits

1.5 CMOS Fabrication and Layout

1.5.1 Inverter Cross-Section

1.5.2 Fabrication Process

1.5.3 Layout Design Rules

1.5.4 Gate Layouts

1.5.5 Stick Diagrams

1.6 Design Partitioning

1.6.1 Design Abstractions

1.6.2 Structured Design

1.6.3 Behavioral,Structural,and Physical Domains

1.7 Example:A Sinple MIPS Microprocessor

1.7.1 MIPS Architecture

1.7.2 Multicycle MIPS Microarchitecture

1.8 Logic Design

1.8.1 Top-Level Interfaces

1.8.2 Block Diagrams

1.8.3 Hierarchy

1.8.4 Hardware Description Languages

1.9 Circuit Design

1.10 Physical Design

1.10.1 Floorplanning

1.10.2 Standard Cells

1.10.3 Pitch Matching

1.10.4 Slice Plans

1.10.5 Arrays

1.10.6 Area Estimation

1.11 Design Veri.cation

1.12 Fabrication,Packaging,and Testing

Summary and a Look Ahead

Exercises

Chapter 2 Devices

2.1 Introduction

2.2 Long-Channel I-V Characteristics

2.3 C-V Characteristics

2.3.1 Simple MOS Capacitance Models

2.3.2 Detailed MOS Gate Capacitance Model

2.3.3 Detailed MOS Diffusion Capacitance Model

2.4 Nonideal I-V Effects

2.4.1 Mobility Degradation and Velocity Saturation

2.4.2 Channel Length Modulation

2.4.3 Threshold Voltage Effects

2.4.4 Leakage

2.4.5 Temperature Dependence

2.4.6 Geometry Dependence

2.4.7 Summary

2.5 DC Transfer Characteristics

2.5.1 Static CMOS Inverter DC Characteristics

2.5.2 Beta Ratio Effects

2.5.3 Noise Margin

2.5.4 Pass Transistor DC Characteristics

2.6 Pitfalls and Fallacies

Summary

Exercises

Chapter 3 Speed

3.1 Introduction

3.1.1 De.nitions

3.1.2 Timing Optimization

3.2 Transient Response

3.3 RC Delay Model

3.3.1 Effective Resistance

3.3.2 Gate and Diffusion Capacitance

3.3.3 Equivalent RC Circuits

3.3.4 Transient Response

3.3.5 Elmore Delay

3.3.6 Layout Dependence of Capacitance

3.3.7 Determining Effective Resistance

3.4 Linear Delay Model

3.4.1 Logical Effort

3.4.2 Parasitic Delay

3.4.3 Delay in a Logic Gate

3.4.4 Drive

3.4.5 Extracting Logical Effort from Datasheets

3.4.6 Limitations to the Linear Delay Model

3.5 Logical Effort of Paths

3.5.1 Delay in Multistage Logic Networks

3.5.2 Choosing the Best Number of Stages

3.5.3 Example

3.5.4 Summary and Observations

3.5.5 Limitations of Logical Effort

3.5.6 Iterative Solutions for Sizing

3.6 Timing Analysis Delay Models

3.6.1 Slope-Based Linear Model

3.6.2 Nonlinear Delay Model

3.6.3 Current Source Model

3.7 Pitfalls and Fallacies

3.8 Historical Perspectives

Summary

Exercises

Chapter 4 Power

4.1 Introduction

4.1.1 De.nitions

4.1.2 Examples

4.1.3 Sources of Power Dissipation

4.2 Dynamic Power

4.2.1 Activity Factor

4.2.2 Capacitance

4.2.3 Voltage

4.2.4 Frequency

4.2.5 Short-Circuit Current

4.2.6 Resonant Circuits

4.3 Static Power

4.3.1 Static Power Sources

4.3.2 Power Gating

4.3.3 Multiple Threshold Voltages and Oxide Thicknesses

4.3.4 Variable Threshold Voltages

4.3.5 Input Vector Control

4.4 Energy-Delay Optimization

4.4.1 Minimum Energy

4.4.2 Minimum Energy-Delay Product

4.4.3 Minimum Energy Under a Delay Constraint

4.5 Low Power Architectures

4.5.1 Microarchitecture

4.5.2 Parallelism and Pipelining

4.5.3 Power Management Modes

4.6 Pitfalls and Fallacies

4.7 Historical Perspective

Summary

Exercises

Chapter 5 Wires

5.1 Introduction

5.1.1 Wire Geometry

5.1.2 Example:Intel Metal Stacks

5.2 Interconnect Modeling

5.2.1 Resistance

5.2.2 Capacitance

5.2.3 Inductance

5.2.4 Skin Effect

5.2.5 Temperature Dependence

5.3 Interconnect Impact

5.3.1 Delay

5.3.2 Energy

5.3.3 Crosstalk

5.3.4 Inductive Effects

5.3.5 An Aside on Effective Resistance and Elmore Delay

5.4 Interconnect Engineering

5.4.1 Width,Spacing,and Layer

5.4.2 Repeaters

5.4.3 Crosstalk Control

5.4.4 Low-Swing Signaling

5.4.5 Regenerators

5.5 Logical Effort with Wires

5.6 Pitfalls and Fallacies

Summary

Exercises

Chapter 6 Scaling,Reliability,and Variability

6.1 Introduction

6.2 Variability

6.2.1 Supply Voltage

6.2.2 Temperature

6.2.3 Process Variation

6.2.4 Design Corners

6.3 Reliability

6.3.1 Reliability Terminology

6.3.2 Oxide Wearout

6.3.3 Interconnect Wearout

6.3.4 Soft Errors

6.3.5 Overvoltage Failure

6.3.6 Latchup

6.4 Scaling

6.4.1 Transistor Scaling

6.4.2 Interconnect Scaling

6.4.3 International Technology Roadmap for Semiconductors

6.4.4 Impacts on Design

6.5 Statistical Analysis of Variability

6.5.1 Properties of Random Variables

6.5.2 Variation Sources

6.5.3 Variation Impacts

6.6 Variation-Tolerant Design

6.6.1 Adaptive Control

6.6.2 Fault Tolerance

6.7 Pitfalls and Fallacies

6.8 Historical Perspective

Summary

Exercises

Chapter 7 SPICE

7.1 Introduction

7.2 A SPICE Tutorial

7.2.1 Sources and Passive Components

7.2.2 Transistor DC Analysis

7.2.3 Inverter Transient Analysis

7.2.4 Subcircuits and Measurement

7.2.5 Optimization

7.2.6 Other HSPICE Commands

7.3 Device Models

7.3.1 Level 1 Models

7.3.2 Level 2 and 3 Models

7.3.3 BSIM Models

7.3.4 Diffusion Capacitance Models

7.3.5 Design Comers

7.4 Device Characterization

7.4.1 I-V Characteristics

7.4.2 Threshold Voltage

7.4.3 Gate Capacitance

7.4.4 Parasitic Capacitance

7.4.5 Effective Resistance

7.4.6 Comparison of Processes

7.4.7 Process and Environmental Sensitivity

7.5 Circuit Characterization

7.5.1 Path Simulations

7.5.2 DC Transfer Characteristics

7.5.3 Logical Effort

7.5.4 Power and Energy

7.5.5 Simulating Mismatches

7.5.6 Monte Carlo Simulation

7.6 Interconnect Simulation

7.7 Pitfalls and Fallacies

Summary

Exercises

Chapter 8 Gates

8.1 Introduction

8.2 Circuit Families

8.2.1 Static CMOS

8.2.2 Ratioed Circuits

8.2.3 Cascode Voltage Switch Logic

8.2.4 Dynamic Circuits

8.2.5 Pass-Transistor Circuits

8.3 Circuit Pitfalls

8.3.1 Threshold Drops

8.3.2 Ratio Failures

8.3.3 Leak age

8.3.4 Charge Sharing

8.3.5 Power Supply Noise

8.3.6 Hot Spots

8.3.7 Minority Carrier Injection

8.3.8 Back-Gate Coupling

8.3.9 Diffusion Input Noise Sensitivity

8.3.10 Process Sensitivity

8.3.11 Example:Domino Noise Budgets

8.4 Silicon-On-Insulator Circuit Design

8.4.1 Floating Body Voltage

8.4.2 SOI Advantages

8.4.3 SOI Disadvantages

8.4.4 Implications for Circuit Styles

8.4.5 Summary

8.5 Subthreshold Circuit Design

8.5.1 Sizing

8.5.2 Gate Selection

8.6 Pitfalls and Fallacies

8.7 Historical Perspective

Summary

Exercises

Chapter 9 Sequencing

9.1 Introduction

9.2 Sequencing Static Circuits

9.2.1 Sequencing Methods

9.2.2 Max-Delay Constraints

9.2.3 Min-Delay Constraints

9.2.4 Time Borrowing

9.2.5 Clock Skew

9.3 Circuit Design of Latches and Flip-Flops

9.3.1 Conventional CMOS Latches

9.3.2 Conventional CMOS Flip-Flops

9.3.3 Pulsed Latches

9.3.4 Resettable Latches and Flip-Flops

9.3.5 Enabled Latches and Flip-Flops

9.3.6 Incorporating Logic into Latches

9.3.7 Klass Semidynamic Flip-Flop(SDFF)

9.3.8 Differential Flip-Flops

9.3.9 Dual Edge-Triggered Flip-Flops

9.3.10 Radiation-Hardened Flip-Flops

9.4 Static Sequencing Element Methodology

9.4.1 Choice of Elements

9.4.2 Characterizing Sequencing Element Delays

9.4.3 State Retention Registers

9.4.4 Level-Converter Flip-Flops

9.4.5 Design Margin and Adaptive Sequential Elements

9.5 Synchronizers

9.5.1 Metastability

9.5.2 A Simple Synchronizer

9.5.3 Communicating Between Asynchronous Clock Domains

9.5.4 Common Synchronizer Mistakes

9.5.5 Arbiters

9.5.6 Degrees of Synchrony

9.6 Wave Pipelining

9.7 Pitfalls and Fallacies

Summary

Exercises

Chapter 10 Datapaths

10.1 Introduction

10.2 Addition/Subtraction

10.2.1 Single-Bit Addition

10.2.2 Carry-Propagate Addition

10.2.3 Subtraction

10.2.4 Multiple-Input Addition

10.2.5 Flagged Prefix Adders

10.3 One/Zero Detectors

10.4 Comparators

10.4.1 Magnitude Comparator

10.4.2 Equality Comparator

10.4.3 K＝A+B Comparator

10.5 Counters

10.5.1 Binary Counters

10.5.2 Fast Binary Counters

10.5.3 Ring and Johnson Counters

10.5.4 Linear-Feedback Shift Registers

10.6 Boolean Logical Operations

10.7 Coding

10.7.1 Parity

10.7.2 Error-Correcting Codes

10.7.3 Gray Codes

10.7.4 XOR/XNOR Circuit Forms

10.8 Shifters

10.8.1 Funnel S hifter

10.8.2 Barrel Shifter

10.8.3 Alternative Shift Functions

10.9 Multiplication

10.9.1 Unsigned Array Multiplication

10.9.2 Two's Complement Array Multiplication

10.9.3 Booth Encoding

10.9.4 Column Addition

10.9.5 Final Addition

10.9.6 Fused Multiply-Add

10.9.7 Summary

10.10 Parallel-Prefix Computations

10.11 Pitfalls and Fallacies

Summary

Exercises

Chapter 11 Memories

11.1 Introduction

11.2 SRAM

11.2.1 SRAM Cells

11.2.2 Row Circuitry

11.2.3 Column Circuitry

11.2.4 Multi-Ported SRAM and Register Files

11.2.5 Large SRAMs

11.2.6 Low-Power SRAMs

11.2.7 Area,Delay,and Power of RAMs and Register Files

11.3 DRAM

11.3.1 Subarray Architectures

11.3.2 Column Circuitry

11.3.3 Embedded DRAM

11.4 Read-Only Memory

11.4.1 Programmable ROMs

11.4.2 NAND ROMs

11.4.3 Flash

11.5 Serial Access Memories

11.5.1 Shift Registers

11.5.2 Queues(FIFO,LIFO)

11.6 Content-Addressable Memory

11.7 Programmable Logic Arrays

11.8 Robust Memory Design

11.8.1 Redundancy

11.8.2 Error Correcting Codes(ECC)

11.8.3 Radiation Hardening

11.9 Historical Perspective

Summary

Exercises

Chapter 12 Packaging,Power,Clock,I/O

12.1 Introduction

12.2 Packaging and Cooling

12.2.1 Package Options

12.2.2 Chip-to-Package Connections

12.2.3 Package Parasitics

12.2.4 Heat Dissipation

12.2.5 Temperature Sensors

12.3 Power Distribution

12.3.1 On-Chip Power Distribution Network

12.3.2 IR Drops

12.3.3 L di/dt Noise

12.3.4 On-Chip Bypass Capacitance

12.3.5 Power Network Modeling

12.3.6 Power Supply Filtering

12.3.7 Charge Pumps

12.3.8 Substrate Noise

12.3.9 Energy Scavenging

12.4 Clocks

12.4.1 De.nitions

12.4.2 Clock System Architecture

12.4.3 Global Clock Generation

12.4.4 Global Clock Distribution

12.4.5 Local Clock Gaters

12.4.6 Clock Skew Budgets

12.4.7 Adaptive Deskewing

12.5 PLLs and DLLs

12.5.1 PLLs

12.5.2 DLLs

12.5.3 Pitfalls

12.6 I/O

12.6.1 Basic I/O Pad Circuits

12.6.2 Electrostatic Discharge Protection

12.6.3 Example:MOSIS I/O Pads

12.6.4 Mixed-Voltage I/O

12.7 High-Speed Links

12.7.1 High-Speed I/O Channels

12.7.2 Channel Noise and Interference

12.7.3 High-Speed Transmitters and Receivers

12.7.4 Synchronous Data Transmission

12.7.5 Clock Recovery in Source-Synchronous Systems

12.7.6 Clock Recovery in Mesochronous Systems

12.7.7 Clock Recovery in Pleisochronous Systems

12.8 Random Circuits

12.8.1 True Random Number Generators

12.8.2 Chip Identification

12.9 Pitfalls and Fallacies

Summary

Exercises

Chapter 13 Methodology

13.1 Introduction

13.2 Structured Design Strategies

13.2.1 A Software Radio—A System Example

13.2.2 Hierarchy

13.2.3 Regularity

13.2.4 Modularity

13.2.5 Locality

13.2.6 Summary

13.3 Design Methods

13.3.1 Microprocessor/DSP

13.3.2 Programmable Logic

13.3.3 Gate Arrayand Sea of Gates Design

13.3.4 Cell-Based Design

13.3.5 Full Custom Design

13.3.6 Platform-Based Design—System on a ChiP

13.3.7 Summary

13.4 Design Flows

13.4.1 Behavioral Synthesis Design Flow(ASIC Design Flow)

13.4.2 Automated Layout Generation

13.4.3 Mixed-Signal or Custom-Design Flow

13.5 Design Economics

13.5.1 Non-Recurring Engineering Costs(NREs)

13.5.2 Recurring Costs

13.5.3 Fixed Costs

13.5.4 Schedule

13.5.5 Personpower

13.5.6 Project Management

13.5.7 Design Reuse

13.6 Data Sheets and Documentation

13.6.1 The Summary

13.6.2 Pinout

13.6.3 Description of Operation

13.6.4 DC Specifications

13.6.5 AC Specifications

13.6.6 Package Diagram

13.6.7 Principles of Operation Manual

13.6.8 User Manual

13.7 Pitfalls and Fallacies

Exercises

Chapter 14 Test

14.1 Introduction

14.1.1 Logic Veri.cation

14.1.2 Debugging

14.1.3 Manufacturing Tests

14.2 Testers,Test Fixtures,and Test Programs

14.2.1 Testers and Test Fixtures

14.2.2 Test Programs

14.2.3 Handlers

14.3 Logic Verification Principles

14.3.1 Test Vectors

14.3.2 Testbenches and Harnesses

14.3.3 Regression Testing

14.3.4 Version Control

14.3.5 Bug Tracking

14.4 Silicon Debug Principles

14.5 Manufacturing Test Principles

14.5.1 Fault Models

14.5.2 Observability

14.5.3 Controllability

14.5.4 Repeatability

14.5.5 Survivability

14.5.6 Fault Coverage

14.5.7 Automatic Test Pattern Generation(ATPG)

14.5.8 Delay Fault Testing

14.6 Design for Testability

14.6.1 Ad Hoc Testing

14.6.2 Scan Design

14.6.3 Built-In Self-Test(BIST)

14.6.4 IDDQ Testing

14.6.5 Design for Manufacturability

14.7 Boundary Scan

14.8 Testing in a University Environment

14.9 Pitfalls and Fallacies

Summary

Exercises

Chapter 15 Fabrication

15.1 Introduction

15.2 CMOS Technologies

15.2.1 Wafer Formation

15.2.2 Photolimography

15.2.3 Well and Channel Formation

15.2.4 Silicon Dioxide(SiO2)

15.2.5 Isolation

15.2.6 Gate Oxide

15.2.7 Gate and Source/Drain Formations

15.2.8 Contacts and Metallization

15.2.9 Passivation

15.2.10 Metrology

15.3 Layout Design Rules

15.3.1 Design Rule Background

15.3.2 Scribe Line and Other Stnctures

15.3.3 MOSIS Scalable CMOS Design Rules

15.3.4 Micron Design Rules

15.4 CMOS Process Enhancements

15.4.1 Transistors

15.4.2 Interconnect

15.4.3 Circuit Elements

15.4.4 Beyond Conventional CMOS

15.5 Technology-Related CAD Issues

15.5.1 Design Rule Checking(DRC)

15.5.2 Circuit Extraction

15.6 Manufacturing Issues

15.6.1 Antenna Rules

15.6.2 LayerDensitv Rules

15.6.3 Resolution Enhancement Rules

15.6.4 Metal Slotting Rules

15.6.5 Yield Enhancement Guidelines

15.7 Pitfalls and Fallacies

15.8 Historical Perspective

Summary

Exercises

References

Index

Credits