1 Digital Systems and VLSI

1.1 Why Design Integrated Circuits?

1.2 Integrated Circuit Manufacturing

1.2.1 Technology

1.2.2 Economics

1.3 CMOS Technology

1.3.1 CMOS Circuit Techniques

1.3.2 Power Consumption

1.3.3 DesignandTestability

1.4 Integrated Circuit Design Techniques

1.4.1 Hierarchical Design

1.4.2 Design Abstraction

1.4.3 Computer-Aided Design

1.5 ALook into the Future

1.6 Summary

1.7 References

1.8 Problems

2 Transistors and Layout

2.1 Introduction

2.2 Fabrication Processes

2.2.1 Overview

2.2.2 Fabrication Steps

2.3 Transistors

2.3.1 Structure of the Transistor

2.3.2 A Simple Transistor Model

2.3.3 Transistor Parasitics

2.3.4 Tub Ties and Latchup

2.3.5 Advanced Transistor Characteristics

2.3.6 Leakage and Subthreshold Currents

2.3.7 Advanced Transistor Structures

2.3.8 Spice Models

2.4 Wires and Vias

2.4.1 Wire Parasitics

2.4.2 Skin Effect in Copper Interconnect

2.5 Design Rules

2.5.1 Fabrication Errors

2.5.2 Scalable Design Rules

2.5.3 SCMOS Design Rules

2.5.4 Typical Process Parameters

2.6 Layout Design and Tools

2.6.1 Layouts for Circuits

2.6.2 Stick Diagrams

2.6.3 Layout Design and Analysis Tools

2.6.4 Automatic Layout

2.7 References

2.8 Problems

3 Logic Gates

3.1 Introduction

3.2 Static Complementary Gates

3.2.1 Gate Structures

3.2.2 Basic Gate Layouts

3.2.3 Logic Levels

3.2.4 Delay and Transition Time

3.2.5 Power Consumption

3.2.6 The Speed-Power Product

3.2.7 Layout and Parasitics

3.2.8 Driving Large Loads

3.3 Switch Logic

3.4 Alternative Gate Circuits

3.4.1 Pseudo-nMOS Logic

3.4.2 DCVS Logic

3.4.3 Domino Logic

3.5 Low-Power Gates

3.6 Delay Through Resistive Interconnect

3.6.1 Delay Through an RC Transmission Line

3.6.2 Delay Through RC Trees

3.6.3 Buffer Insertion in RC Transmission Lines

3.6.4 Crosstalk Between RC Wires

3.7 Delay Through Inductive Interconnect

3.7.1 RLC Basics

3.7.2 RLC Transmission Line Delay

3.7.3 Buffer Insertion in RLC Transmission Lines

3.8 References

3.9 Problems

4 Combinational Logic Networks

4.1 Introduction

4.2 Standard Cell-Based Layout

4.2.1 Single-Row Layout Design

4.2.2 Standard Cell Layout Design

4.3 Simulation

4.4 Combinational Network Delay

4.4.1 Fanout

4.4.2 Path Delay

4.4.3 Transistor Sizing

4.4.4 Automated Logic Optimization

4.5 Logic and Interconnect Design

4.5.1 Delay Modeling

4.5.2 Wire Sizing

4.5.3 Buffer Insertion

4.5.4 Crosstalk Minimization

4.6 Power Optimization

4.6.1 Power Analysis

4.7 Switch Logic Networks

4.8 Combinational Logic Testing

4.8.1 Gate Testing

4.8.2 Combinational Network Testing

4.9 References

4.10 Problems

5 Sequential Machines

5.1 Introduction

5.2 Latches and Flip-Flops

5.2.1 Categories of Memory Elements

5.2.2 Latches

5.2.3 Flip-Flops

5.3 Sequential Systems and Clocking Disciplines

5.3.1 One-Phase Systems for Flip-Flops

5.3.2 Two-Phase Systems for Latches

5.3.3 Advanced Clocking Analysis

5.3.4 Clock Generation

5.4 Sequential System Design

5.4.1 Structural Specification of Sequential Machines

5.4.2 State Transition Graphs and Tables

5.4.3 State Assignment

5.5 Power Optimization

5.6 Design Validation

5.7 Sequential Testing

5.8 References

5.9 Problems

6 Subsystem Design

6.1 Introduction

6.2 Subsystem Design Principles

6.2.1 Pipelining

6.2.2 Data Paths

6.3 Combinational Shifters

6.4 Adders

6.5 ALUs

6.6 Multipliers

6.7 High-Density Memory

6.7.1 ROM

6.7.2 Static RAM

6.7.3 The Three-Transistor Dynamic RAM

6.7.4 The One-Transistor Dynamic RAM

6.8 References

6.9 Problems

7 Floorplanning

7.1 Introduction

7.2 Floorplanning Methods

7.2.1 Block Placement and Channel Definition

7.2.2 Global Routing

7.2.3 Switchbox Routing

7.2.4 Power Distribution

7.2.5 Clock Distribution

7.2.6 Floorplanning Tips

7.2.7 Design Validation

7.3 Off-Chip Connections

7.3.1 Packages

7.3.2 The I/O Architecture

7.3.3 Pad Design

7.4 References

7.5 Problems

8 Architecture Design

8.1 Introduction

8.2 Hardware Description Languages

8.2.1 Modeling with Hardware Description Languages

8.2.2 VHDL

8.2.3 Verilog

8.2.4 C as a Hardware Description Language

8.3 Register-Transfer Design

8.3.1 Data Path-Controller Architectures

8.3.2 ASM ChartDesign

8.4 High-Level Synthesis

8.4.1 Functional Modeling Programs

8.4.2 Data

8.4.3 Control

8.4.4 Dataand Control

8.4.5 Design Methodology

8.5 Architectures for Low Power

8.5.1 Architecture-Driven Voltage Scaling

8.5.2 Power-Down Modes

8.6 Systems-on-Chips and Embedded CPUs

8.7 Architecture Testing

8.8 References

8.9 Problems

9 Chip Design

9.1 Introduction

9.2 Design Methodologies

9.3 Kitchen Timer Chip

9.3.1 Timer Specification and Architecture

9.3.2 Architecture Design

9.3.3 Logic and Layout Design

9.3.4 Design Validation

9.4 Microprocessor Data Path

9.4.1 Data Path Organization

9.4.2 Clocking and Bus Design

9.4.3 Logic and Layout Design

9.5 References

9.6 Problems

10 CAD Systems and Algorithms

10.1 Introduction

10.2 CAD Systems

10.3 Switch-Level Simulation

10.4 Layout Synthesis

10.4.1 Placement

10.4.2 Global Routing

10.4.3 Detailed Routing

10.5 Layout Analysis

10.6 Tuning Analysis and Optimization

10.7 Logic Synthesis

10.7.1 Technology-Independent Logic Optimization

10.7.2 Technology-Dependent Logic Optimizations

10.8 Test Generation

10.9 Sequential Machine Optimizations

10.10 Scheduling and Binding

10.11 Hardware/Software Co-Design

10.12 References

10.13 Problems

A Chip Designer's Lexicon

B Chip Design Projects

B.1 Class Project Ideas

B.2 Project Proposal and Specification

B.3 Design Plan

B.4 Design Checkpoints and Documentation

B.4.1 Subsystems Check

B.4.2 First Layout Check

B.4.3 Project Completion

C Kitchen Timer Model

C.1 Hardware Modeling in C

C.1.1 Simulator

C.1.2 Sample Execution

References

Index