1 Fundamentals of Computer Design

References

E．1 Implementation Issues for the Snooping Coherence Protocol

Appendix E:Implementing Coherence Protocols

D．1 Introduction

Appendix D:An Alternative to RISC: The Intel 80x86

C．1 Introduction

Appendix C: Survey of Risc Architectures

B．1 Why Vector Processors?

Appendix B:Vector Processors

A．1 Introduction

Xerox Paio Alto Research Center

by DAVID GOLDBERG

Appendix A: Computer Arithmetic

Index

1．1 Introduction

D．2 80x86 Registers and Data Addressing Modes

A．2 Basic Techniques of Integer Arithmetic

C．2 Addressing Modes and Instruction Formats

1．2 The Task of a Computer Designer

B．2 Basic Vector Architecture

C．3 Instructions : The DLX Subset

E．2 Implementation Issues in the Distributed Directory Protocol

1．3 Technology and Computer Usage Trends

D．3 80x86 Integer Operations

1．4 Cost and Trends in Cost

D．4 80x86 Floating-Point Operations

C．4 Instructions : Common Extensions to DLX

D．5 80x86 Instruction Encoding

Exercises

C．5 Instructions Unique to MIPS

A．3 Floating Point

B．3 Two Real-World Issues : Vector Length and Stride

C．6 Instructions Unique to SPARC

D．6 Putting It All Together : Measurements of Instruction Set Usage

A．4 Floating-Point Multiplication

C．7 Instructions Unique to PowerPC

1．5 Measuring and Reporting Performance

C．8 Instructions Unique to PA-RISC

D．7 Concluding Remarks

B．4 Effectiveness of Compiler Vectorization

A．5 Floating-Point Addition

C．9 Concluding Remarks

B．5 Enhancing Vector Performance

D．8 Historical Perspective and References

C．10 References

A．6 Division and Remainder

B．6 Putting It All Together : Performance of Vector Processors

1．6 Quantitative Principles of Computer Design

A．7More on Floating-Point Arithmetic

B．7 Fallacies and Pitfalls

B．8 Concluding Remarks

A．8 Speeding Up Integer Addition

B．9 Historical Perspective and References

1．7 Putting it All Together:The Concept of Memory Hierarchy

Exercises

1．8 Fallacies and Pitfalls

A．9 Speeding Up Integer Multiplication and Division

1．9 Concluding Remarks

1．10 Historical Perspective and References

Exercises

A．10 Putting It All Together

A．11 Fallacies and Pit?alls

A．12 Historical Perspective and References

2．1 Introduction

2 Instruction Set Principles and Examples

2．2 Classifying Instruction Set Architecfures

Exercises

2．3 Memory Addressing

2．4 Operations in the Instruction Set

2．5 Type and Size of Operands

2．6 Encoding an Instruction Set

2．7 Crosscutting Issues:The Role of Compilers

2．8 Putting it All Together : The DLX Architecture

2．9 Fallacies and Pitfalls

2．10 Concluding Remarks

2．11 Historical Perspective and References

Exercises

3．1 What Is Pipelining?

3 Pipellning

3．2 The Basic Pipeline for DLX

3．3 The Major Hurdle of Pipelining ——Pipeline Hazards

3．4 Data Hazards

3．5 Control Hazards

3．6 What Makes Pipelining Hard to Implement?

3．7 Extending the Dlx Pipeline to Handle Multicycle Operations

3．8 Crosscutting Issues : Instruction Set Design and Pipelining

3．9 Putting It All Together: The MIPS R4000 Pipeline

3．10 Fallacies and Pitfalls

3．11 Concluding Remarks

3．12 Historical Perspective and References

Exercises

4．1 Instruction-Level Parallelism : Concepts and Challenges

4 Advanced Pipelining and Instruction-Level Parallelism

4．2 Overcoming Data Hazards with Dynamic Scheduling

4．3 Reducing Branch Penalties with Dynamic Hardware Prediction

4．4 Taking Advantage of More ILP with Multiple Issue

4．5 Compiler Support for Exploiting ILP

4．6 Hardware Support for Extracting More Parallelism

4．7 Studies of ILP

4．8 Putting It All Together : The PowerPC 620

4．9 Fallacies and Pitfalls

4．10 Concluding Remarks

4．11 Historical Perspective and References

Exercises

5．1 Introduction

5 Memory-Hierarchy Design

5．2 The ABCs of Caches

5．3 Reducing Cache Misses

5．4 Reducing Cache Miss Penalty

5．5 Reducing Hit Time

5．6 Main Memory

5．7 Virtual Memory

5．8 Protection and Examples of Virtual Memory

5．9 Crosscutting Issues in the Design of Memory Hierarchies

5．10 Putting It All Together: The Alpha AXP 21064 Memory Hierarchy

5．11 Fallacies and Pitfalls

5．12 Concluding Remarks

5．13 Historical Perspective and References

Exercises

6．1 Introduction

6 Storage Systems

6．2 Types of Storage Devices

6．3 Buses-Connecting I/O Devices to CPU/Memory

6．4 I/O Performance Measures

6．5 Reliability, Availability, and RAID

6．6 Crosscutting Issues : Interfacing to an Operating System

6．7 Designing an I/O System

6．8 Putting It All Together: UNIX File System Performance

6．9 Fallacies and Pitfalls

6．10 Concluding Remarks

6．11Historical Perspective and References

Exercises

7 Interconnection Networks

7．1 Introduction

7．2 A Simple Network

7．3 Connecting the Interconnection Network to the Computer

7．4 Interconnection Network Media

7．5 Connecting More Than Two Computers

7．6 Practical Issues for Commercial Interconnection Networks

7．7 Examples of Interconnection Networks

7．8 Crosscutting Issues for Interconnection Networks

7．9 Intemetworking

7．10 Putting It All TOgether : An ATM Network of Workstations

7．11 Fallacies and Pitfalls

7．12 Concluding Remarks

7．13 Historical Perspective and References

Exercises

8 Multiprocessors

8．1 Introduction

8．2 Characteristics of Application Domains

8．3 Centralized Shared-Memory Architectures

8．4 Distributed Shared-Memory Architectures

8．5 Synchronization

8．6 Models of Memory Consistency

8．7 Crosscutting Issues

8．8 Putting It All Together : The SGI Challenge Multiprocessor

8．9 Fallacies and Pitfalls

8．10 Concluding Remarks

8．11 Historical Perspective and References

Exercises