1 Introduction to Analog Design

1.1 Why Analog？

1.2 Why Integrated？

1.3 Why CMOS？

1.4 Why This Book？

1.5 General Concepts

1.5.1 Levels of Abstraction

1.5.2 Robust Analog Design

2 Basic MOS Device Physics

2.1 General Considerations

2.1.1 MOSFET as a Switch

2.1.2 MOSFET Structure

2.1.3 MOS Symbols

2.2 MOS I/V Characteristics

2.2.1 Threshold Voltage

2.2.2 Derivation of I/V Characteristics

2.3 Second-Order Effects

2.4 MOS Device Models

2.4.1 MOS Device Layout

2.4.2 MOS Device Capacitances

2.4.3 MOS Small-Signal Model

2.4.4 MOS SPICE models

2.4.5 NMOS versus PMOS Devices

2.4.6 Long-Channel versus Short-Channel Devices

3 Single-Stage Amplifiers

3.1 Basic Concepts

3.2 Common-Source Stage

3.2.1 Common-Source Stage with Resistive Load

3.2.2 CS Stage with Diode-Connected Load

3.2.3 CS Stage with Current-Source Load

3.2.4 CS Stage with Triode Load

3.2.5 CS Stage with Source Degeneration

3.3 Source Follower

3.4 Common-Gate Stage

3.5 Cascode Stage

3.5.1 Folded Cascode

3.6 Choice of Device Models

4 Differential Amplifiers

4.1 Single-Ended and Differential Operation

4.2 Basic Differential Pair

4.2.1 Qualitative Analysis

4.2.2 Quantitative Analysis

4.3 Common-Mode Response

4.4 Differential Pair with MOS Loads

4.5 Gilbert Cell

5 Passive and Active Current Mirrors

5.1 Basic Current Mirrors

5.2 Cascode Current Mirrors

5.3 Active Current Mirrors

5.3.1 Large-Signal Analysis

5.3.2 Small-Signal Analysis

5.3.3 Common-Mode Properties

6 Frequency Response of Amplifiers

6.1 General Considerations

6.1.1 Miller Effect

6.1.2 Association of Poles with Nodes

6.2 Common-Source Stage

6.3 Source Followers

6.4 Common-Gate Stage

6.5 Cascode Stage

6.6 Differential Pair

Appendix A：Dual of Miller’s Theorem

7 Noise

7.1 Statistical Characteristics of Noise

7.1.1 Noise Spectrum

7.1.2 Amplitude Distribution

7.1.3 Correlated and Uncorrelated Sources

7.2 Types of Noise

7.2.1 Thermal Noise

7.2.2 Flicker Noise

7.3 Representation of Noise in Circuits

7.4 Noise in Single-Stage Amplifiers

7.4.1 Common-Source Stage

7.4.2 Common-Gate Stage

7.4.3 Source Followers

7.4.4 Cascode Stage

7.5 Noise in Differential Pairs

7.6 Noise Bandwidth

8 Feedback

8.1 General Considerations

8.1.1 Properties of Feedback Circuits

8.1.2 Types of Amplifiers

8.2 Feedback Topologies

8.2.1 Voltage-Voltage Feedback

8.2.2 Current-Voltage Feedback

8.2.3 Voltage-Current Feedback

8.2.4 Current-Current Feedback

8.3 Effect of Loading

8.3.1 Two-Port Network Models

8.3.2 Loading in Voltage-Voltage Feedback

8.3.3 Loading in Current-Voltage Feedback

8.3.4 Loading in Voltage-Current Feedback

8.3.5 Loading in Current-Current Feedback

8.3.6 Summary of Loading Effects

8.4 Effect of Feedback on Noise

9 Operational Amplifiers

9.1 General Considerations

9.1.1 Performance Parameters

9.2 One-Stage Op Amps

9.3 Two-Stage Op Amps

9.4 Gain Boosting

9.5 Comparison

9.6 Common-Mode Feedback

9.7 Input Range Limitations

9.8 Slew Rate

9.9 Power Supply Rejection

9.10 Noise in Op Amps

10 Stability and Frequency Compensation

10.1 General Considerations

10.2 Multipole Systems

10.3 Phase Margin

10.4 Frequency Compensation

10.5 Compensation of Two-Stage Op Amps

10.5.1 Slewing in Two-Stage Op Amps

10.6 Other Compensation Techniques

11 Bandgap References

11.1 General Considerations

11.2 Supply-Independent Biasing

11.3 Temperature-Independent References

11.3.1 Negative-TC Voltage

11.3.2 Positive-TC Voltage

11.3.3 Bandgap Reference

11.4 PTAT Current Generation

11.5 Constant-Gm Biasing

11.6 Speed and Noise Issues

11.7 Case Study

12 Introduction to Switched-Capacitor Circuits

12.1 General Considerations

12.2 Sampling Switches

12.2.1 MOSFETS as Switches

12.2.2 Speed Considerations

12.2.3 Precision Considerations

12.2.4 Charge Injection Cancellation

12.3 Switched-Capacitor Amplifiers

12.3.1 Unity-Gain Sampler/Buffer

12.3.2 Noninverting Amplifier

12.3.3 Precision Multiply-by-Two Circuit

12.4 Switched-Capacitor Integrator

12.5 Switched-Capacitor Common-Mode Feedback

13 Nonlinearity and Mismatch

13.1 Nonlinearity

13.1.1 General Considerations

13.1.2 Nonlinearity of Differential Circuits

13.1.3 Effect of Negative Feedback on Nonlinearity

13.1.4 Capacitor Nonlinearity

13.1.5 Linearization Techniques

13.2 Mismatch

13.2.1 Offset Cancellation Techniques

13.2.2 Reduction of Noise by Offset Cancellation

13.2.3 Alternative Definition of CMRR

14 Oscillators

14.1 General Considerations

14.2 Ring Oscillators

14.3 LC Oscillators

14.3.1 Crossed-Coupled Oscillator

14.3.2 Colpitts Oscillator

14.3.3 One-Port Oscillators

14.4 Voltage-Controlled Oscillators

14.4.1 Tuning in Ring Oscillators

14.4.2 Tuning in LC Oscillators

14.5 Mathematical Model of VCOs

15 Phase-Locked Loops

15.1 Simple PLL

15.1.1 Phase Detector

15.1.2 Basic PLL Topology

15.1.3 Dynamics of Simple PLL

15.2 Charge-Pump PLLs

15.2.1 Problem of Lock Acquisition

15.2.2 Phase/Frequency Detector and Charge Pump

15.2.3 Basic Charge-Pump PLL

15.3 Nonideal Effects in PLLs

15.3.1 PFD/CP Nonidealities

15.3.2 Jitter in PLLs

15.4 Delay-Locked Loops

15.5 Applications

15.5.1 Frequency Multiplication and Synthesis

15.5.2 Skew Reduction

15.5.3 Jitter Reduction

Appendix A Short-Channel Effects and Device Models

A.1 Scaling Theory

A.2 Short-Channel Effects

A.2.1 Threshold Voltage Variation

A.2.2 Mobility Degradation with Vertical Field

A.2.3 Velocity Saturation

A.2.4 Hot Carrier Effects

A.2.5 Output Impedance Variation with Drain-Source Voltage

A.3 MOS Device Models

A.3.1 Level 1 Model

A.3.2 Level 2 Model

A.3.3 Level 3 Model

A.3.4 BSM Series

A.3.5 Other Models

A.3.6 Charge and Capacitance Modeling

A.3.7 Temperature Dependence

A.4 Process Corners

A.5 Analog Design in a Digital World

Appendix B CMOS Processing Technology

B.1 General Considerations

B.2 Wafer Processing

B.3 Photolithography

B.4 Oxidation

B.5 Ion Implantation

B.6 Deposition and Etching

B.7 Device Fabrication

B.7.1 Active Devices

B.7.2 Passive Devices

B.7.3 Interconnects

B.8 Latch-Up

Appendix C Layout and Packaging

C.1 General Layout Considerations

C.1.1 Design Rules

C.1.2 Antenna Effect

C.2 Analog Layout Techniques

C.2.1 Multifinger Transistors

C.2.2 Symmetry

C.2.3 Reference Distribution

C.2.4 Passive Devices

C.2.5 Interconnects

C.3 Substrate Coupling

Index